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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr xr16c850 2.97v to 5.5v uart with 128-byte fifo august 2005 rev. 2.3.1 general description the xr16c850 1 (850) is a universal asynchronous receiver and transmitter (uart). this device supports intel and pc mode data bus interface and is software compatible to industry standard 16c450, 16c550, st16c580 and st16c650a uarts. the 850 has 128 bytes of tx and rx fifos and is capable of operating up to a serial data rate of 2 mbps. the internal registers include the 16c550 register set plus exar?s enhanced registers for additional features to support today?s highly demanding data communication needs. the enhanced features include automatic hardware and software flow control, selectable tx and rx trigger levels, and wireless infrared (irda) encoder/decoder. the xr16c850 is available in the 44 pin plcc and 48 pin tqfp packages. they both provide the standard intel bus mode and pc isa bus (pc) mode. the intel bus mode is compatible with the st16c450 and st16c550 while the pc mode allows connection to the pc isa bus. n ote : 1 covered by u.s. patent #5,649,122 and #5,949,787. features added feature in devices with top mark date code of "f2 yyww" and newer: 5 volt tolerant inputs 0 ns address hold time (t ah ) ? 2.97 to 5.5 volt operation ? pin to pin compatible to st16c550, st16c580, st16c650a and tl16c750 ? 128-byte transmit and receive fifos ? transmit/receive fifo counters ? programmable tx/rx fifo trigger levels ? automatic hardware/sof tware flow control ? auto rs-485 half duplex direction support ? programmable xon/xoff characters ? infrared (irda) tx and rx encoder/decoder ? sleep mode (100 ua stand-by) applications ? battery operated electronics ? internet appliances ? handheld terminal ? personal digital assistants ? cellular phones dataport ? wireless infrared data communications systems f igure 1. b lock d iagram xtal1/clk xtal2 crystal osc/buffer dtr#, rts# dsr#, cts#, cd#, ri# intel or pc data bus interface 128 byte tx fifo baud rate generator infrared encoder transmitter uart configuration regs ior ior# 128 byte rx fifo infrared decoder receiver modem control signals tx rx cts flow control rts flow control brg prescaler cs1 cs0 ddis# int txrdy# rxrdy# a2:a0 d7:d0 iow cs2# pcmode# s1 s2 s3 irqa irqb irqc iow # reset pc mode: com 1 to 4 decode logic
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 2 f igure 2. p inouts i n i ntel b us m ode a nd pc m ode , tqfp a nd plcc p ackages 44-plcc package 48-tqfp package 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 n.c. d5 d6 d7 rclk n.c. rx tx cs0 cs1 -cs2 -baudout clksel xtal1 xtal2 iow# iow gnd ior# ior n.c. as# sel reset op1#/rs485 dtr# rts# op2# int rxrdy# a0 a1 a2 bus 8/16 n.c. d4 d3 d2 d1 d0 vcc ri# cd# dsr# cts# n.c. xr16c850cm intel bus mode (sel = vcc) 8-bit bus mode ddis# txrdy# 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 n.c. d5 d6 d7 s2 a4 rx tx a5 a6 a7 lpt1# clksel xtal1 xtal2 iow# a8 gnd ior# a3 s1 lpt2# irqc aen# sel reset op1#/rs485 dtr# rts# s3 irqa irqb a0 a1 a2 bus 8/16 n.c. d4 d3 d2 d1 d0 vcc ri# cd# dsr# cts# a9 xr16c850cm pc mode (sel = gnd) 8-bit bus mode only 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 d11 d5 d6 d7 rclk n.c. rx tx cs0 cs1 -cs2 -baudout clksel xtal1 xtal2 iow# iow gnd ior# ior n.c. as# sel reset op1#/rs485 dtr# rts# op2# int rxrdy# a0 a1 a2 bus 8/16 d10 d4 d3 d2 d1 d0 vcc ri# cd# dsr# cts# n.c. xr16c850cm intel bus mode (sel = vcc) 16-bit bus mode d12 txrdy# 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 d5 d6 d7 rclk rx n.c. tx cs0 cs1 cs2# baudout# reset op1#/rs485 dtr# rts# op2# sel int rxrdy# a0 a1 a2 d4 d3 d2 d1 d0 n.c. vcc ri# cd# dsr# cts# xtal1 xtal2 iow# iow gnd n.c. ior# ior ddis# txrdy# as# xr16c850cj intel bus mode (sel = vcc) 8-bit bus mode only 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 d5 d6 d7 s2 rx a4 tx a5 a6 a7 lpt1# reset op1#/rs485 dtr# rts# s3 sel irqa irqb a0 a1 a2 d4 d3 d2 d1 d0 a9 vcc ri# cd# dsr# cts# xtal1 xtal2 iow# a8 gnd s1 ior# a3 lpt2# irqc aen# xr16c850cj pc mode (sel = gnd) 8-bit bus mode only
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 3 pin descriptions n ote : pin type: i=input, o=output, io= input/output, od=output open drain. ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus xr16c850cj 44-lead plcc 0c to +70c active xr16c850cm 48-lead tqfp 0c to +70c active xr16c850ij 44-lead plcc -40c to +85c active xr16c850im 48-lead tqfp -40c to +85c active n ame 44-p in plcc 48-p in tqfp t ype d escription i ntel b us m ode i nterface . t he sel pin is connected to vcc. a2 a1 a0 29 30 31 26 27 28 i address data lines [2:0]. a2:a0 selects internal uart?s configuration registers. d0 d1 d2 d3 d4 d5 d6 d7 2 3 4 5 6 7 8 9 43 44 45 46 47 2 3 4 i/o data bus lines [7:0] (bidirectional). ior# 24 19 i input/output read (active low). the fallin g edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [a2:a0], places it on the data bus to allo w the host processor to read it on the lead - ing edge. either an active ior# or ior is required to transfer data from 850 to cpu during a read operation. if not used, co nnect this pin to vcc. caution: see?fac - tory test mode? on page 7. ior 25 20 i input/output read (active high). same as ior# but active high. either an active ior# or ior is required to transfer data from 850 to cpu during a read operation. if not used, connect this pin to gnd. during pc mode, this pin becomes a3. cau - tion: see?factory test mode? on page 7. iow# 20 16 i input/output write (active low). the falli ng edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines [a2:a0]. either an active iow# or iow is required to transfer data from 850 to the intel type cp u during a write oper ation. if not used, connect this pin to vcc. caution: see?factory test mode? on page 7. iow 21 17 i input/output write (active high). the risi ng edge instigates the internal write cycle and the falling edge transfers the data byte on the data bus to an internal register pointed by the address lines [a2:a0]. either an active iow# or iow is required to transfer data from 850 to the intel type cp u during a write operation. during pc mode, this pin becomes a8. if not used, connect this pin to gnd. caution: see?factory test mode? on page 7.
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 4 cs0 14 9 i chip select 0 input (active high). this input selects the xr16c850 device. if cs1 or cs2# is used as the chip select then this pin must be connected to vcc. during pc mode, this pin becomes a5. caution: see?factory test mode? on page 7. cs1 15 10 i chip select 1 input (active high). this input selects the xr16c850 device. if cs0 or cs2# is used as the chip select then this pin must be connected to vcc. during pc mode, this pin becomes a6. caution: see?factory test mode? on page 7. cs2# 16 11 i chip select 2 input (active low). this inpu t selects the xr16c850 device. if cs0 or cs1 is used as the chip select then this pin must be connected to gnd. during pc mode, this pin becomes a7. caution: see?factory test mode? on page 7. int 33 30 o interrupt output. this output becomes active whenever the transmitter, receiver, line and/or modem status register has an ac tive condition and is enabled by ier. see interrupt section for more details. during pc mode, this pin becomes irqa. rxrdy# 32 29 o receive ready (active low). a logic 0 indicates receive data ready status, i.e. the rhr is full or the fifo has one or more rx characters available for unloading. for details, see table 2 . during pc mode, this pin becomes irqb. txrdy# 27 23 o transmit ready (active low). buffer ready st atus is indicated by a logic 0, i.e. at least one location is empty and available in the fifo or thr. for details, see table 2 . during pc mode, th is pin becomes irqc. as# 28 24 i address strobe input (active low). in the intel bus mode, the leading-edge transition of as# latches the chip selects (cs0, cs1, cs2#) and the address lines a0, a1 and a2. this input is used when the address lines are not stable for the duration of a read or write operation. in devices with top mark date code of "f2 yyww" and newer, the address bus is latched even if this input is not used. these devices fea - ture a ?0 ns? address hold time. see ?ac electrical characteristics? . if not required, this input can be permanent ly tied to gnd. during pc mode, this pin becomes aen#. d10 d11 d12 - - - 48 1 22 o high order data bus. when bus8/16 is select ed as 16 bit data bus mode (bus8/16 is grounded), rx data errors (break, parity, framing) can be read via these pins. d10 = parity, d11 = framing, and d12 = break. when bus8/16 is selected as 8 bit data bus mode (bus8/16 is at vcc), d10 and d11 are inactive and d12 becomes ddis#. during pc mode, d10 and d11 are inactive and d12 becomes lpt2#. bus8/16 - 25 i 8 or 16 bit bus select. for normal 8 bit operation, this pin should be connected to vcc or left open. to select 16 bit bus mode, this pin should be connected to gnd. when 16 bit bus mode is enabled, ddis# becomes d12. 16 bit bus mode is not available for pc mode. only rx data erro r will be provided during this operation. this pin has an internal pull-up resistor. clksel - 13 i clock select. the div-by-1 or div-by-4 pre-scaleable clock is selected by this pin. the div-by-1 clock is selected when clksel is connected to vcc or the div-by-4 is selected when clksel is connected to gnd. mcr bit-7 c an override the state of this pin following reset or initialization (s ee mcr bit-7). this pin is not available on 40 and 44 pin packages which provide mcr bit-7 selection only. this pin has an internal pull-up resistor. rclk 10 5 i this input is used as external 16x clock input to the receiver section. if not used, connect the -baudout pin to this input externally. during pc mode, this pin becomes s2. n ame 44-p in plcc 48-p in tqfp t ype d escription
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 5 baud - out# 17 12 o baud rate generator output (active low). this pin provides the 16x clock of the selected data rate from the baud rate ge nerator. the rclk pin must be connected externally to baudout# when the receiver is operating at the same data rate. when the pc mode is selected, the baud rate generator clock output is internally connected to the rclk input. this pin then functions as the printer port decode logic output (lpt1#), see table 3 . ddis# 26 22 o drive disable output. this pin goes to a logic 0 whenever the host cpu is reading data from the 850. it can control the direction of a data bus transceiver between the cpu and 850 or other logic functions. if 16 bit bus mode is selected, this pin becomes d12. during pc mode, this pin becomes lpt2#. op2# 35 31 o output port 2. general pu rpose output. during pc mo de, this pin becomes s3. pc m ode i nterface s ignals . c onnect sel pin to gnd to select pc m ode . a3 25 20 i address-3 select bit. this pin is used as the 4th address line to decode the com1-4 and lpt ports. see table 1 for details. during intel bus mode, this pin becomes ior. a4 12 6 i address-4 select bit. this pin is used as the 5th address line to decode the com1-4 and lpt ports. this pin has an internal 100k ? pull-up resistor. this pin is not available on the 40-pin pdip package which operates in the intel bus mode only. see table 1 for details. during intel bus mode, this pin is inactive. a5 a6 a7 a8 14 15 16 21 9 10 11 17 i address-5 thru address-8 se lect bit. these pins are used as the 6th thru 9th address lines to decode the com1-4 and lpt ports. see table 1 for details. dur - ing intel bus mode, a5 becomes cs0, a6 becomes cs1, a7 becomes cs2#, and a8 becomes iow. a9 1 37 i address-9 select bit. this pin is used as the 10th address line to decode the com1-4 and lpt ports. this pin has an internal 100k ? pull-up resistor. this pin is not available on the 40-pin pdip package which operates in the intel bus mode only. see table 1 for details. during intel bus mode, this pin is inactive. aen# 28 24 i address enable input (active low). when aen# transitions to logic 0, it decodes and validates com 1-4 ports address per s1, s2 and s3 inputs. during intel bus mode, this pin becomes as#. s1 s2 s3 23 10 35 21 5 31 i select 1 to 3. these are the standard pc com 1-4 ports and irq selection inputs. see table 1 and table 3 for details. the s1 pin has an internal 100k ? pull-up resistor. this pin is not available on the 40 pin pdip packages which operates in the intel bus mode only. during intel bus mode, s1 is inactive, s2 becomes rclk, and s3 becomes op2#. irqa irqb irqc 33 32 27 30 29 23 o interrupt request a, b and c outputs (a ctive high, three-state). these are the interrupt outputs associated with com 1-4 to be connected to the host data bus. see interrupt section for details. the in terrupt requests a, b or c functions as irqx to the pc bus. irqx is enabled by setting mcr bit-3 to logic 1 and the desired interrupt(s) in the interrupt enable register (ier). du ring intel bus mode, irqa becomes int, irqb becomes rxrdy#, and irqc becomes txrdy#. lpt1# 17 12 o line printer port-1 decode logic output (active low). this pin functions as the pc standard lpt-1 printer port address decode logic output, see table 1 . the baud rate generator clock output, baudout#, is internally connected to the rclk input in the pc mode. during intel bus mode, lpt1# becomes baudout#. n ame 44-p in plcc 48-p in tqfp t ype d escription
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 6 lpt2# 26 22 o line printer port-2 decode logic output (act ive low) - this pin functions as the pc standard lpt-2 printer port address decode logic output, see table 1 . during intel bus mode, lpt2# becomes ddis#/d12. modem or serial i/o interface tx 13 8 o transmit data or wireless infrared transmit data. this output is active low in normal standard serial interface operation (rs-232, rs-422 or rs-485) and active high in the infrared mode. infrared mode can be enabled by connecting pin enir to vcc or through software selection after power up. rx 11 7 i receive data or wireless infrared receive data. normal received data input idles at logic 1 condition and logic 0 in the infrar ed mode. the wireless infrared pulses are applied to the decoder. this input must be co nnected to its idle logic state in either normal, logic 1, or infrared mode, logic 0, else the receiver may report ?receive break? and/or ?error? condition(s). rts# 36 32 o request to send or general purpose output (active low). this port may be used for automatic hardware flow control, see efr bit-6, mcr bit-1, fctr bits 0-1 and ier bit-6. rts# output must be asserted before auto rts flow control can start. if this pin is not needed for modem communication, t hen it can be used as a general i/o. if it is not used, leave it unconnected. cts# 40 38 i clear to send or general purpose input (a ctive low). if used for automatic hardware flow control, data transmission will be stopped when this pin is de-asserted and will resume when this pin is asserted again. see efr bit-7, mcr bit-2 and ier bit-7. if this pin is not needed for modem communica tion, then it can be used as a general i/o. if it is not used, connect it to vcc. dtr# 37 33 o data terminal ready or general purpose output (active low). if this pin is not needed for modem communication, then it can be used as a general i/o. if it is not used, leave it unconnected. dsr# 41 39 i data set ready input or general purpose input (active low). if this pin is not needed for modem communication, then it can be used as a general i/o. if it is not used, connect it to vcc. cd# 42 40 i carrier detect input or general purpose input (active low). if this pin is not needed for modem communication, then it can be us ed as a general i/o. if it is not used, connect it to vcc. ri# 43 41 i ring indicator input or general purpose input (active low). if this pin is not needed for modem communication, then it can be us ed as a general i/o. if it is not used, connect it to vcc. ancillary signals xtal1 18 14 i crystal or external clock input. see figure 7 for typical oscillator connections. caution: this input is not 5v tolerant. xtal2 19 15 o crystal or buffered clock output. see figure 7 for typical oscillator connections. sel 34 36 i pc mode select (active low). when this i nput is at logic 0, it enables the on-board chip select decode function according to pc isa bus com[4:1] and irq[4,3] port definitions. see table 3 for details. this pin has an internal 100k ? pull-up resistor. this pin is not available on the 40 pin pdip packages which operate in the intel bus mode only. n ame 44-p in plcc 48-p in tqfp t ype d escription
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 7 pin type: i=input, o=output, i/o= input/output, od=output open drain. factory test mode for devices with top mark date code of "ec yyww" and older devices, please note that if ior# (or ior) and iow# (or iow) are both as serted simultaneously, the 850 will enter a factory test mode. the most noticeable factory test mode symptom is the cont inuous transmission of the same c haracter on the tx pin. this usually happens during power-up or when another device in th e design requires both signals to be asserted simultaneously (like an sdram). a soluti on to this would be to or (and if using active-high signals) the chip selects with the read and write signals to the xr16c850 as shown below: for devices with top mark date code of "f2 yyww" and hi gher devices, the solution for the factory test mode given in the figure above ha s been incorporated into the uart. it will only enter factory test mode when all three signals (chip select, read and write) are asserted simultaneously. op1#/ rs485 38 34 o output port 1 (general purpose output) or rs-485 direction control signal. rs- 485 direction control can be selected when fctr bit-3 is set to ?1?. during data transmit cycle, rs485 pin is low. an invert er is usually required before connecting to rs-485 transceiver. reset 39 35 i reset input (active high). when it is assert ed, the uart configur ation registers are reset to default values, see table 15 . vcc 44 42 pwr power supply input. all inputs are 5v tolerant except for xtal1 for devices with top mark date code of "f2 yyww" and newer. devices with top mark date code of "ec yyww" and older do not have 5v tolerant inputs. gnd 22 18 pwr power supply common ground. n ame 44-p in plcc 48-p in tqfp t ype d escription cs2# ior# iow# cs0 or cs1 ior iow (active low signals) (active high signals) cs# ior# iow# cs ior iow (from cpu or pld) (from cpu or pld) xr16c850 xr16c850
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 8 1.0 product description the xr16c850 (850) provides serial asynchronous receive data synchronization, parallel-to-serial and serial- to-parallel data conversions for both the transmitter and receiver sections. these functions are necessary for converting the serial data stream in to parallel data that is required with digital data systems. synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). data integr ity is ensured by attaching a parity bit to the data character. the parity bit is checked by the receiver for any transmission bit errors. the electronic circuitry to provide all these functions is fairly complex especially when ma nufactured on a single integrated silicon chip. the xr16c850 represents such an integration with greatl y enhanced features. the 850 is fabricated using an advanced cmos process. enhanced features the 850 is an upward solution that provides 128 bytes of transmit and receive fifo memory, instead of 32 bytes provided in the 16c650a, 16 bytes in the 16c550 , or none in the 16c450. the 850 is designed to work with high speed modems and shared network environments, that require fast data processing time. increased performance is realized in the 850 by the larger transmi t and receive fifos. this allows the external processor to handle more networking tasks within a given time. fo r example, the st16c550 with a 16 byte fifo, unloads 16 bytes of receive data in 1.53 ms (this example uses a character length of 11 bits, including start/stop bits at 115.2kbps). this means the external cpu will have to serv ice the receive fifo at 1. 53 ms intervals. however with the 128 byte fifo in the 850, th e data buffer will not require unloading/l oading for 12.2 ms. this increases the service interval giving the external cpu additional time for other applications and reducing the overall uart interrupt servicing ti me. in addition, the programmable fifo trigger level interrupt and automatic hardware/software flow control is uniquely prov ided for maximum data throughput performance. the combination of the above greatly reduces the bandwidth requirem ent of the external controlling cpu, increases performance, and reduces power consumption. the 850 provides a rs-485 half-duplex direction cont rol signal, pin op1#/rs485 to select the external transceiver direction. it automatically changes the state of the output pin for receive state after the last stop-bit of the last character has been shifted out of the tx sh ift register. afterward, upon loading a tx data byte, it changes state of the output pin back for transmit state. the rs-485 direct ion control pin is not activated after reset. to activate the direction control function, the user has to set efr bit-4, and fctr bit-3 to ?1?. this pin (op1#/rs485) is high for receive state, low for transmit state. data bus interface two data bus interfaces are available to the user. the pc mode allows direct interconnect to the pc isa bus while the intel bus mode operates similar to the stan dard cpu interface available on the 16c450/550/650a. when the pc mode is selected, the external logic circuitry required for pc com port address decode and chip select is eliminated. these functions are provided internally in the 850. data rate the 850 is capable of operation up to 1.5 mbps with a 24 mhz crystal or external clock input with a 16x sampling clock. however, it is possible to operate up to 2.25 mbps with a 36 mhz exter nal clock for devices with top mark date code of "f2 yyww" and newer, and up to 2 mbps with a 33 mhz external clock for devices with top mark date code of "ec yyww" and older. with a crystal of 14.7456 mhz and through a software option, the user can select data rates up to 921.6 kbps. the rich feature set of the 850 is available through intern al registers. automatic hardware/software flow control, selectable transmit and receive fifo trigger levels, selectable tx and rx baud rates, infrared encoder/ decoder interface, modem interface controls, and a sleep mode are all standard features. in addition, there is a pc mode that has two additional three state interrupt lines and one selectable open source interrupt output. the open source interrupt scheme allows multiple interrupts to be combined in a ?wire-or? operation, thus reducing the number of interrupt lines in larger systems. following a power on reset or an external reset, the 850 is software compatible with previous gene ration of uarts, 16c450 and 16c550 and 16c650a.
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 9 2.0 functional descriptions 2.1 host data bus interface the host interface is 8 data bits wide with 3 address li nes and control signals to execute bus read and write transactions. the 850 supports 2 types of host interf aces: intel and pc mode. the intel bus interface is selected by connecting sel to logic 1. when the sel pin is set to a logic 1, the 850 interface is the same as industry standard 16c550. the intel bus interconnections are shown in figure 3 . the special pc mode is selected when sel is connected to logic 0. the pc mode interconnections are shown in figure 4 . . f igure 3. xr16c850 i ntel b us i nterconnections f igure 4. xr16c850 pc m ode i nterconnections d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 ior iow reset d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# a0 a1 a2 cs2# reset vcc cs0 cs1 as# ior iow int int rclk baudout# sel vcc gnd cs# op2# op1# dsr# cts# rts# dtr# rx tx ri# cd# d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 a7 a14 a15 aen# iow# ior# reset d0 d1 d2 d3 d4 d5 d6 d7 iow# a0 a1 a2 reset vcc irqn irqa sel vcc gnd ior# irqb irqc irq4 irq3 a3 a4 a5 a6 a7 a8 a9 aen op1# ri# cd# dsr# cts# rx tx rts# dtr# s1 s2 s3 vcc gnd gnd
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 10 2.2 pc mode the pc mode interface includes an on-chip address deco der and interrupt selection function for the standard pc com 1-4 ports addresses. the selection is made thr ough three input signals: s1, s2 and s3. the selection summary is shown in table 1 . although the on-chip address decoder was designed for pc applications ranging from 0x278 to 0x3ff, it can fit into an embedded applications by offsetting the address lines to the 850. an example is shown in figure 5 where the uart is operating from 0x80f8 to 0x80ff address space. operating in the pc mode eliminates external address decode components. t able 1: pc m ode i nterface o n - chip a ddress d ecoder and i nterrupt s election . sel# input s3, s2, s1 i nputs a3-a9 a ddress l ines to o n - chip d ecoder com/lpt p ort s election irq o utput s election 0 0 0 0 0x3f8 - 0x3ff com-1 irqb (for pc?s irq4) 0 0 0 1 0x2f8 - 0x2ff com-2 irqc (for pc?s irq3) 0 0 1 0 0x3e8 - 0x3ef com-3 irqb (for pc?s irq4) 0 0 0 0 0x3f8 - 0x3ff com-4 irqb (for pc?s irq4) 0 1 0 0 0x2f8 - 0x2ff com-1 irqa (for pc?s irqn 0 1 0 1 0x3e8 - 0x3ef com-2 irqa (for pc?s irqn) 0 1 1 0 0x2e8 - 0x2ef com-3 irqa (for pc?s irqn) 0 1 1 1 0x3f8 - 0x3ff com-4 irqa (for pc?s irqn) 0 x x x 0x278 - 0x27f lpt-2 n/a 0 x x x 0x378 - 0x37f lpt-1 n/a f igure 5. pc m ode i nterface in an e mbedded a pplication . d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 a7 a14 a15 aen# iow # ior# reset d0 d1 d2 d3 d4 d5 d6 d7 io w # a0 a1 a2 reset vcc int irq a sel vcc gnd io r# irq b irq c a3 a4 a5 a6 a7 a8 a9 aen* op1# ri# cd# dsr# cts# rx tx rts# dtr# s1 s2 s3 vcc gnd gnd embedded application set to operate at address 0x80f8 to 0x80ff
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 11 2.3 16-bit bus interface the 16-bit bus interface is only available on the 48 pi n package. the 16-bit bus mode is enabled when the bus8/16 pin is connected to gnd. in this mode, the rx data errors can be read via the higher order data bus pins d10-d12. see figure 6 . 2.4 5-volt tolerant inputs for devices that have top mark date code "f2 yyww" an d newer, the 850 can accept a voltage of up to 5.5v on any of its inputs (except xtal1) when operating from 2.97v to 5.5v. xtal1 is not 5 volt tolerant. devices that have top mark date code "ec yyww" and older do not have 5v tolerant inputs. 2.5 device reset the reset input resets the internal registers and the serial interface outputsto their default state (see ta b l e 15 ). an active high pulse of longer than 40 ns duration will be required to activate the reset function in the device. 2.6 device identification and revision the xr16c850 provides a device identification code and a device revision code to distinguish the part from other devices and revisions. to read the identification code from the part, it is required to set the baud rate generator regist ers dll and dlm both to 0x00. now reading the content of the dlm will provide 0x10 for the xr16c850 and reading the content of dll will provide th e revision of the part; for example, a reading of 0x01 means revision a. f igure 6. xr16c850 16-b it b us i nterface d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 ior iow reset d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# a0 a1 a2 cs2# reset vcc cs0 cs1 as# ior iow int int rclk baudout# sel vcc gnd cs# op2# op1# dsr# cts# rts# dtr# rx tx ri# cd# parity error framing error break error d11 d12 d10 bus8/16
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 12 2.7 internal registers the 850 has a set of enhanced registers for controlli ng, monitoring and data loading and unloading. the configuration register set is compatib le to those already available in the standard 16c550. these registers function as data holding registers (thr/rhr), interrupt status and control registers (isr/ier), a fifo control register (fcr), receive line status and control regist ers (lsr/lcr), modem status and control registers (msr/ mcr), programmable data rate (clock) divisor registers (dll/dlm), and a user accessible scractchpad register (spr). beyond the general 16c550 fe atures and capabilities, t he 850 offers enha nced feature regist ers (emsr, trg, fc, fctr, efr, xon/xoff 1, xon/xoff 2) that provide automatic rts and cts hardware flow control, xon/xoff software flow control, automatic rs- 485 half-duplex direction output enable/di sable, fifo trigge r level control, and fifo level counters. all the register functions are discussed in full detail later in ?section 3.0, uart internal registers? on page 25 . 2.8 dma mode the dma mode (a legacy term) in this document does not mean ?direct memory access? but refers to data block transfer operation. the dma mode affects the st ate of the rxrdy# a/b and txrdy# a/b output pins. the transmit and receive fifo trigger levels provide additional flexib ility to the user for block mode operation. the lsr bits 5-6 provide an indication when the transmitte r is empty or has an empty location(s) for more data. the user can optionally operate the transmit and re ceive fifo in the dma mode (fcr bit-3=1). when the transmit and receive fifo are enabled and the dma mode is disabled (fcr bit-3 = 0), the 850 activates the interrupt output pin for each data transmit or receive operation. when dma mode is enabled (fcr bit-3 = 1), the user takes advantage of block mode operation by loading or unloading the fifo in a block sequence determined by the programmed trigger level. in this mode, the 850 sets the txrdy# pin when the transmit fifo becomes full, and sets the rxrdy# pin when the receive fifo becomes empty. the following table shows their behavior. t able 2: txrdy# and rxrdy# o utputs in fifo and dma m ode p ins fcr bit -0=0 (fifo d isabled ) fcr b it -0=1 (fifo e nabled ) fcr bit-3 = 0 (dma mode disabled) fcr bit-3 = 1 (dma mode enabled) rxrdy# a/b 0 = 1 byte. 1 = no data. 0 = at least 1 byte in fifo 1 = fifo empty. 1 to 0 transition when fifo reaches the trigger level, or timeout occurs. 0 to 1 transition when fifo empties. txrdy# a/b 0 = thr empty. 1 = byte in thr. 0 = fifo empty. 1 = at least 1 byte in fifo. 0 = fifo has at least 1 empty location. 1 = fifo is full.
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 13 2.9 interrupts the output function of interrupt outputs change according to the operating bus type. during the intel bus mode, the int output will always be active high and mcr bit- 3 will have no effect on the int output pin. in the pc mode, the irq outputs are in three-state mode unless mcr bit-3 and s3 are both a logic 1. table 3 summarizes its behavior in intel and pc mode of operation. 2.10 crystal oscillator or external clock the 850 includes an on-chip oscillator (xtal1 and xtal2) . the crystal oscillator provides the system clock to the baud rate generators (brg ) in the uart. xtal1 is the input to the oscillator or external clock buffer input with xtal2 pin being the output. for programming details, see ?section 2.11, programmable baud rate generator? on page 14 . to use the same clock for the receiver as used with the transmiter of the uart in the intel bus mode, the baudclk pin must be connec ted to the rclk pin external to the uart. the on-chip oscillator is designed to use an industry stand ard microprocessor cryst al (parallel resonant, fundamental frequency with 10-22 pf capacitance load, esr of 20-120 ohms and 100ppm frequency tolerance) connected externally between the xtal1 and xtal2 pins (see figure 7 ). alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for standard or custom rates. typically, the oscillator connections are shown in figure 7 . for further reading on os cillator circuit please see application note dan108 on exar?s web site. t able 3: i nterrupt o utput f unctions b us m ode mcr b it -3 s3 (pc m ode o nly ) i nterrupt o utput (int or irq) intel x x active high pc 0 0 three-state 0 1 three-state 1 0 three-state 1 1 active high f igure 7. t ypical oscillator connections c1 22-47pf c2 22-47pf y1 1.8432 mhz to 24 mhz r1 0-120 (optional) r2 500k - 1m xtal1 xtal2
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 14 2.11 programmable baud rate generator the uart has its own baud rate ge nerator (brg) with a prescaler for th e transmitter. the prescaler is controlled by a software bit in the mcr register. the mcr register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4. the clock output of the prescaler goes to the brg. the brg further divides this clock by a programmable divisor between 1 and (2 16 -1) to obtain a 16x sampling clock of the serial data rate. the sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. the brg divisor (dll and dlm registers) defaults to a random value upon power up or a reset. therefore, the brg must be programmed during initialization to the operating data rate. programming the ba ud rate generator regi sters dlm and dll provides th e capability of selecting the operating data rate. table 4 shows the standard data rates availabl e with a 14.7456 mhz crystal or external clock at 16x clock rate. when using a non-standard data rate crystal or external clock, the divisor value can be calculated for dll/dlm with the following equation. f igure 8. b aud r ate g enerator divisor (decimal) = (xtal1 clock frequency / prescaler) / (serial data rate x 16) t able 4: t ypical data rates with a 14.7456 mh z crystal or external clock o utput data rate mcr bit-7=1 o utput data rate mcr bit-7=0 d ivisor for 16x clock (decimal) d ivisor for 16x clock (hex) dlm p rogram v alue (hex) dll p rogram v alue (hex) d ata r ate e rror (%) 100 400 2304 900 09 00 0 600 2400 384 180 01 80 0 1200 4800 192 c0 00 c0 0 2400 9600 96 60 00 60 0 4800 19.2k 48 30 00 30 0 9600 38.4k 24 18 00 18 0 19.2k 76.8k 12 0c 00 0c 0 38.4k 153.6k 6 06 00 06 0 57.6k 230.4k 4 04 00 04 0 115.2k 460.8k 2 02 00 02 0 230.4k 921.6k 1 01 00 01 0 xtal1 xtal2 crystal osc/ buffer mcr bit-7=0 (default) mcr bit-7=1 dll and dlm registers prescaler divide by 1 prescaler divide by 4 16x sampling rate clock to transmitter and receiver baud rate generator logic clksel = vcc clksel = gnd during initialization or reset
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 15 2.12 transmitter the transmitter section comp rises of an 8-bit transmit shift register (tsr) and 128 bytes of fifo which includes a byte-wide transmit holding register (thr). tsr shifts out every data bit with the 16x internal clock. a bit time is 16 clock periods. the transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop -bit(s). the status of the fifo and tsr are reported in the line status register (lsr bit-5 and bit-6). 2.12.1 transmit holding re gister (thr) - write only the transmit holding register is an 8-bit register pr oviding a data interface to the host processor. the host writes transmit data byte to the thr to be converted in to a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-si gnificant-bit (bit-0) becomes first data bit to go out. the thr is the input register to the transmit fifo of 12 8 bytes when fifo operation is enabled by fcr bit-0. every time a write operation is made to the thr, the fifo data pointer is automatically bumped to the next sequential data location. 2.12.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a transmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr beco mes completely empty. 2.12.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 128 bytes of transmit data. the thr empt y flag (lsr bit-5) is set whenever the fifo is empty. the thr empty flag can ge nerate a transmit empty interrupt (isr bit-1) when the amount of data in the fifo falls below its programmed trig ger level. the transmit empty interrupt is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr/fifo becomes empty. f igure 9. t ransmitter o peration in non -fifo m ode transmit holding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x clock
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 16 2.13 receiver the receiver section contains an 8-bit receive shift re gister (rsr) and 128 bytes of fifo which includes a byte-wide receive holding register (rhr). the rsr uses the 16x clock for timing. it verifies and validates every bit on the incoming char acter in the middle of each da ta bit. on the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16x clock rate. after 8 clocks the start bit period should be at the center of the start bit. at this time the start bit is sampled an d if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false character. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. if there were any error(s), they are reported in the lsr register bits 2- 4. upon unloading the receive data byte from rhr, the receive fifo pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in rhr register. rhr can generate a receive data re ady interrupt upon receiving a character or delay until it reaches the fifo trigger level. furthermore, data deliv ery to the host is guaranteed by a receive data ready time-out interrupt when data is not rece ived for 4 word lengths as defined by lcr[1:0] plus 12 bits time. this is equivalent to 3.7-4.6 character times. the rhr interrupt is enabled by ier bit-0. 2.13.1 receive holding regi ster (rhr) - read-only the receive holding register is an 8-bit register that holds a receive data byte from the receive shift register. it provides the receive data interface to the host processor. the rhr register is part of the receive fifo of 128 bytes by 11-bits wide, the 3 extra bits are fo r the 3 error tags to be reported in lsr register. when the fifo is enabled by fcr bit-0, the rhr contains the first data character received by the fifo. after the rhr is read, the next character byte is loaded into the rhr and the errors associated with the current data byte are immediately updated in the lsr bits 2-4. f igure 10. t ransmitter o peration in fifo and f low c ontrol m ode transmit data shift register (tsr) transmit data byte thr interrupt (isr bit-1) falls below the programmed trigger level and then when becomes empty. fifo is enabled by fcr bit-0=1 transmit fifo 16x clock auto cts flow control (cts# pin) auto software flow control flow control characters (xoff1/2 and xon1/2 reg. txfifo1
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 17 n ote : table-b selected as trigger table for figure 12 ( table 10 ). f igure 11. r eceiver o peration in non -fifo m ode f igure 12. r eceiver o peration in fifo and a uto rts f low c ontrol m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 16x clock receive data characters data bit validation error tags in lsr bits 4:2 receive data shift register (rsr) rxfifo1 16x clock error tags (128-sets) error tags in lsr bits 4:2 128 bytes by 11-bit wide fifo receive data characters fifo trigger=16 example : - rx fifo trigger level selected at 16 bytes (see note below) data fills to 24 data falls to 8 data bit validation receive data fifo receive data receive data byte and errors rhr interrupt (isr bit-2) programmed for desired fifo trigger level. fifo is enabled by fcr bit-0=1 rts# de-asserts when data fills above the flow control trigger level to suspend remote transmitter. enable by efr bit-6=1, mcr bit-1. rts# re-asserts when data falls below the flow control trigger level to restart remote transmitter. enable by efr bit-6=1, mcr bit-1.
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 18 2.14 auto rts (hardware) flow control automatic rts hardware flow control is used to prevent data overrun to the local receiver fifo. the rts# output is used to request remote unit to suspend/r esume data transmission. the auto rts flow control features is enabled to fit specific application requirement (see figure 13 ): ? enable auto rts flow control using efr bit-6. ? the auto rts function must be started by asserting rts# output pin (mcr bit-1 to logic 1 after it is enabled). ? enable rts interrupt through ier bit-6 (after setting efr bit-4). the uart issues an interrupt when the rts# pin makes a transition from low to high: isr bit-5 will be set to logic 1. 2.15 auto rts hysteresis the 850 has a new feature th at provides flow control trigger hyster esis while it maintains compatibility to 16c650a and 16c550. with the auto rts function enab led, an interrupt is genera ted when the receive fifo reaches the programmed rx tr igger level. the rts# pin will not be fo rced to a logic 1 (rts off), until the receive fifo reaches the upper limit of the hysteresis level. the rts# pi n will return to a logic 0 after the rx fifo is unloaded to the lo wer limit of the hysteresis level. under the above described c onditions, the 850 will continue to accept data until the receive fifo gets full. the auto rts function is initiated when the rts# output pin is asserted to a logic 0 (rts on). for complete details, see table 5 . t able 5: a uto rts h ysteresis t rigger t able s elected (s ee t able 10 ) fctr b it -1 fctr b it -0 t rigger l evel (c haracters ) rts h ysteresis (c haracters ) int p in a ctivation rts# d e -a sserted (c haracters ) rts# a sserted (c haracters ) trigger table-a 0 0 1 - 1 4 0 0 0 4 - 4 8 1 0 0 8 - 8 14 4 0 0 14 - 14 14 8 trigger table-b 0 0 8 - 8 16 0 0 0 16 - 16 24 8 0 0 24 - 24 28 16 0 0 28 - 28 28 24 trigger table-c 0 0 8 - 8 16 0 0 0 16 - 16 56 8 0 0 56 - 56 60 16 0 0 60 - 60 60 56 trigger table-d (programmable) 0 1 n 4 n n + 4 n - 4 1 0 n 6 n n + 6 n - 6 1 1 n 8 n n + 8 n - 8
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 19 2.16 auto cts (hardware) flow control automatic cts flow control is used to prevent data overrun to the remote receiver fifo. the cts# input is monitored to suspend/restart the local transmitter. the aut o cts flow control feature is selected to fit specific application requirement (see figure 13 ): ? enable auto cts flow control using efr bit-7. ? enable cts interrupt through ier bit-7 (after setting efr bit-4). the uart issues an interrupt when the cts# pin is de-asserted (logic 1): isr bit-5 will be set to 1, and uart will suspend transmission as soon as the stop bit of the character in process is shifted ou t. transmission is resumed after the cts# input is re- asserted (logic 0), indicating more data may be sent. f igure 13. a uto rts and cts f low c ontrol o peration the local uart (uarta) starts data transfer by asserting rtsa# (1). rtsa# is normally connected to ctsb# (2) of remote uart (uartb). ctsb# allows its transmitter to se nd data (3). txb data arrives and fills uarta receive fifo (4). when rxa data fills up to its receive fifo trigger le vel, uarta activates its rxa data ready interrupt (5) and con - tinues to receive and put data into its fifo. if interrupt se rvice latency is long and data is not being unloaded, uarta monitors its receive data fill level to match the upper thre shold of rts delay and de-assert rtsa# (6). ctsb# follows (7) and request uartb transmitter to suspend data transfer. ua rtb stops or finishes sending the data bits in its trans - mit shift register (8). when receive fifo data in uarta is unloaded to match the lower threshold of rts delay (9), uarta re-asserts rtsa# (10), ctsb# recognizes the change (11) and restarts its transmitter and data flow again until next receive fifo trigger (12). this same event applies to the reverse direction when uarta sends data to uartb with rtsb# and ctsa# controlling the data flow. rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold data starts on off on assert rts# to begin transmission 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12 rtscts1
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 20 2.17 auto xon/xoff (software) flow control when software flow control is enabled ( see table 14 ), the 850 compares one or two sequential receive data characters with the programmed xon or xoff-1,2 charac ter value(s). if receive character(s) (rx) match the programmed values, the 850 will halt tr ansmission (tx) as soon as th e current characte r has completed transmission. when a match occurs, the xoff (if enabled vi a ier bit-5) flag will be set and the interrupt output pin will be activated. following a su spension due to a match of the xoff character, the 850 will monitor the receive data stream for a match to the xon-1,2 character. if a match is found, the 850 will resume operation and clear the flags (isr bit-4). reset initially sets the contents of the xon/xoff 8-bit flow control registers to a logic 0. following reset the user can write any xon/xoff value desired for software flow c ontrol. different conditions can be set to detect xon/ xoff characters ( see table 14 ) and suspend/resume transmissions. when double 8-bit xon/xoff characters are selected, the 850 compares two consec utive receive characters with two software flow control 8-bit values (xon1, xon2, xoff1, xoff2) and controls tx transmissi ons accordingly. under the above described flow control mechanisms, flow control characters are not placed (sta cked) in the user accessible rx data buffer or fifo. in the event that the receive buffer is overfilling and flow control needs to be executed, the 850 automatically sends an xoff message (when enabled) via the serial tx output to the remote modem. the 850 sends the xoff- 1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate) after the receive fifo crosses the programmed trigger level (for all trigger tables a-d). to clear this condition, the 850 will transmit the programmed xon-1,2 characters as soon as receive fi fo is less than one trigger level below the programmed trigger le vel (for trigger tables a, b, and c) or when receive fifo is less than the trigger level minus the hysteresis value (for trigger tabl e d). this hysteresis value is the same as the auto rts hysteresis value in table 5 . table 6 below explains this when trigger table-b (see table 10 ) is selected. * after the trigger level is reached, an xoff character is se nt after a short span of time (= time required to send 2 characters); for example, after 2.083ms has el apsed for 9600 baud and 10-bit word length setting. 2.18 special character detect a special character detect feature is provided to detect an 8-bit character when bit-5 is set in the enhanced feature register (efr). when this character (xoff2) is detected, it will be placed in the fi fo along with normal incoming rx data. the 850 compares each inco ming receive character with xo ff-2 data. if a match exists, the received data will be transferred to fifo and is r bit-4 will be set to indicate detection of special character. al though the internal register table shows xon, xoff registers with eight bits of character information, the actual number of bits is dependent on the programmed word lengt h. line control register (lcr) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. the word length selected by lcr bits 0-1 also determines the number of bits that will be used for the special character comparison. bit-0 in the xon, xoff registers corresponds with the ls b bit for the receive character. 2.19 auto rs485 half-duplex control the auto rs485 half-duplex direction control changes th e behavior of the transmitter when enabled by mcr bit-2. it de-asserts op1#/rs485 output following the last stop bit of the last character that has been transmitted. this helps in turning around the transceiver to receive the remote station?s response. when the host is ready to transmit next polling data packet again, it only has to load data bytes to the transmit fifo. the transmitter automatically re-asserts op1# output prior to sending the data. see figure 14 . t able 6: a uto x on /x off (s oftware ) f low c ontrol rx t rigger l evel int p in a ctivation x off c haracter ( s ) s ent ( characters in rx fifo ) x on c haracter ( s ) s ent ( characters in rx fifo ) 8 8 8* 0 16 16 16* 8 24 24 24* 16 28 28 28* 24
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 21 2.20 infrared mode the 850 uart includes the infrared encoder and decoder compatible to the irda (infrared data association) version 1.0. the irda 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide high- pulse for each ?0? bit in the transmit data stream. this signal encoding reduces the on-time of the infrared led, hence reduces the power consumption. see figure 15 . the infrared encoder and decoder are enabled by setting mcr register bit-6 to a ?1?. when the infrared feature is enabled, the transmit data output, tx, idles at logic zero level. likewise, the rx input assumes an idle level of logic zero from a reset and power up, see figure 15 . typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the rx pin. each time it senses a light pulse, it returns a logic 1 to the data bit stream. however, this is not true with some infrared modules on the market which indicate a logic 0 by a light pulse. so the 850 has a provision to invert the input polarity to accomodate this. in this case, the user can enable fctr bit-2 to invert the incoming infrared rx signal. f igure 14. a uto rs-485 h alf -d uplex c ontrol d rs-485 transceiver r tx op1#/rs485 rx t+ t- r+ r- 850 uart (0 = transmit 1= receive)
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 22 f igure 15. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding character data bits start stop 0000 0 11 111 bit time 1/16 clock delay irdecoder-1 rx data receive ir pulse (rx pin) (fctr bit-2 = 0) character data bits start stop 0000 0 11 111 tx data transmit ir pulse (tx pin) bit time 1/2 bit time 3/16 bit time irencoder-1 character data bits start stop 0000 0 11 111 bit time 1/16 clock delay irdecoder-1 rx data receive ir pulse (rx pin) (fctr bit-2 = 1)
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 23 2.21 sleep mode with auto wake-up the 850 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. all of these conditions must be sati sfied for the 850 to enter sleep mode: no interrupts pending for the 850 (isr bit-0 = 1) sleep mode is enabled (ier bit-4 = 1) modem inputs are not toggling (msr bits 0-3 = 0) rx input pin is idling at a logic 1 the 850 stops its crystal oscillator to conserve power in the sl eep mode. user can che ck the xtal2 pin for no clock output as an indication that the device has entered the sleep mode. the 850 resumes normal operation by any of the following: a receive data start bit transition (logic 1 to 0) a data byte is loaded to the transmitter, thr or fifo a change of logic state on any of the modem or general purpose serial inputs: cts#, dsr#, cd#, ri# if the 850 is awakened by any one of the above conditions , it will return to the sleep mode automatically after all interrupting conditions have been serviced and clea red. if the 850 is awakened by the modem inputs, a read to the msr is required to reset th e modem inputs. in any ca se, the sleep mode will not be entered while an interrupt is pending. the 850 will stay in the sleep mode of operation until it is disabl ed by setting ier bit-4 to a logic 0. if the address lines, data bus lines, iow#, ior#, csa#, csb#, and modem input lines remain steady when the 850 is in sleep mode, the maximum cu rrent will be in the microamp range as specified in the dc electrical characteristics on page 42 . if the input lines are floating or are toggling while the 850 is in sleep mode, the current can be up to 100 times more. if any of those signals are toggling or floating, then an external buffer would be required to keep the address, data and control lines steady to achieve the low current. a word of caution: owing to the star ting up delay of the crystal oscillato r after waking up from sleep mode, the first few receive characters may be lost . also, make sure the rx input is idling at logic 1 or ?marking? condition during sleep mode. this may not occur when the external interface transceivers (rs-232, rs-485 or another type) are also put to sleep mode and cannot maintain th e ?marking? condition. to avoid this, the system design engineer can use a 47k ohm pull-up resistor on the rx input.
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 24 2.22 internal loopback the 850 uart provides an internal loopback capability for system di agnostic purposes. t he internal loopback mode is enabled by setting mcr register bit-4 to logic 1. all regular uart functions operate normally. figure 16 shows how the modem port signals are re-configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to re ceive the same data that it was sending. the tx pin is held at logic 1 or mark condition while rts# and dtr# are de-asserted, and cts#, dsr# cd# and ri# inputs are ig nored. caution: the rx input must be held to a logic 1 during loopback test else upon exiting the loopback test the uart may detect and report a false ?break? signal. f igure 16. i nternal l oopback tx rx modem / general purpose control logic internal data bus lines and control signals rts# mcr bit-4=1 vcc vcc transmit shift register (thr/fifo) receive shift register (rhr/fifo) cts# dtr# dsr# ri# cd# op1# op2# rts# cts# dtr# dsr# ri# cd# vcc vcc op2# vcc op1#
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 25 3.0 uart internal registers the 850 has a set of configuration registers selected by address lines a0, a1 and a2. the 16c550 compatible registers can be accessed when lcr[7] = 0 and the baud rate generator divisor registers can be accessed when lcr[7] = 1 and lcr 0xbf. the enhanced registers are accessible only when lcr = 0xbf. the complete register set is shown on table 7 and table 8 . t able 7: xr16c850 uart internal registers a2,a1,a0 a ddresses r egister r ead /w rite c omments 16c550 c ompatible r egisters 0 0 0 rhr - receive holding register thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 dll - div latch low byte read/write lcr[7] = 1, lcr 0xbf 0 0 1 dlm - div latch high byte read/write 0 0 0 drev - device revision code read-only dll, dlm = 0x00, lcr[7] = 1, lcr 0xbf 0 0 1 dvid - device identification code read-only 0 0 1 ier - interrupt enable register read/write lcr[7] = 0 0 1 0 isr - interrupt status register fcr - fifo control register read-only write-only 0 1 1 lcr - line control register read/write 1 0 0 mcr - modem control register read/write lcr[7] = 0 1 0 1 lsr - line status register reserved read-only write-only 1 1 0 msr - modem status register reserved read-only write-only 1 1 1 spr - scratch pad register read/write lcr[7] = 0, fctr[6] = 0 1 1 1 flvl - tx/rx fifo level counter register read-only lcr[7] = 0, fctr[6] = 1 1 1 1 emsr - enhanced mode select register write-only e nhanced r egisters 0 0 0 trg - tx/rx fifo trigger level reg fc - tx/rx fifo level counter register write-only read-only lcr = 0xbf 0 0 1 fctr - feature control reg read/write 0 1 0 efr - enhanced function reg read/write 1 0 0 xon-1 - xon character 1 read/write 1 0 1 xon-2 - xon character 2 read/write 1 1 0 xoff-1 - xoff character 1 read/write 1 1 1 xoff-2 - xoff character 2 read/write
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 26 . t able 8: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 16c550 compatible registers 0 0 0 rhr rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 0 0 0 0 thr wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier rd/wr 0/ 0/ 0/ 0/ modem status int. enable rx line status - int. enable tx empty int. enable rx data int. enable cts# int. enable rts# int. enable xoff int.. enable sleep mode enable 0 1 0 isr rd fifos enabled fifos enabled 0/ 0/ int source bit-3 int source bit-2 int source bit-1 int source bit-0 int source bit-5 int source bit-4 0 1 0 fcr wr rx fifo trigger rx fifo trigger 0/ 0/ dma mode enable tx fifo reset rx fifo reset fifos enable tx fifo trigger tx fifo trigger 0 1 1 lcr rd/wr divisor enable set tx break set parity even parity parity enable stop bits word length bit-1 word length bit-0 1 0 0 mcr rd/wr 0/ 0/ 0/ internal lopback enable op2#/ int output enable op1#/ auto rs485 output rts# output control dtr# output control lcr[7] = 0 brg pres - caler ir mode enable xonany 1 0 1 lsr rd rx fifo global error thr & tsr empty thr empty rx break rx framing error rx parity error rx over - run error rx data ready 1 1 0 msr rd cd# input ri# input dsr# input cts# input delta cd# delta ri# delta dsr# delta cts# 1 1 1 spr rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 0 fctr[6]=0 1 1 1 emsr wr rsvd rsvd rsvd rsvd rsvd rsvd rx/tx fifo count rx/tx fifo count lcr[7] = 0 fctr[6]=1 1 1 1 flvl rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 baud rate generator divisor 0 0 0 dll rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 1 lcr 0xbf 0 0 1 dlm rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 27 4.0 internal register descriptions 4.1 receive holding register (rhr) - read- only see?receiver? on page 16. 4.2 transmit holding register (thr) - write-only see?transmitter? on page 15. 4.3 interrupt enable register (ier) - read/write the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are r eported in the interrupt status register (isr). 4.3.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = 1) and receive interr upts (ier bit-0 = 1) are enabled, the rhr interrupts (see isr bits 2 and 3) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b. fifo level will be reflected in the isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared wh en the fifo drops below the trigger level. c. the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is rese t when the fifo is empty. 0 0 0 drev rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 1 lcr 0xbf dll=0x00 dlm=0x00 0 0 1 dvid rd 0 0 0 1 0 0 0 0 enhanced registers 0 0 0 trg wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr=0 x bf 0 0 0 fc rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 fctr rd/wr rx/tx mode scpad swap trig ta b l e bit-1 trig ta b l e bit-0 auto rs485 direction control rx ir input inv. auto rts hyst bit-1 auto rts hyst bit-0 0 1 0 efr rd/wr auto cts enable auto rts enable special char select enable ier [7:4], isr [5:4], fcr[5:4], mcr[7:5] soft- ware flow cntl bit-3 soft - ware flow cntl bit-2 soft - ware flow cntl bit-1 soft - ware flow cntl bit-0 1 0 0 xon1 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 xon2 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 0 xoff1 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 xoff2 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 t able 8: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 28 4.3.2 ier versus receive/transmit fifo polled mode operation when fcr bit-0 equals a logic 1 for fifo enable; rese tting ier bits 0-3 enables the xr16c850 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit-1 indicates an overrun error has occurred and that data in the fifo may not be valid. c. lsr bit 2-4 provides the type of receive data erro rs encountered for the data byte in rhr, if any. d. lsr bit-5 indicates thr is empty. e. lsr bit-6 indicates when both the transmit fifo and tsr are empty. f. lsr bit-7 indicates a data error in at least one character in the rx fifo. ier[0]: rhr interrupt enable the receive data ready interrupt will be issued when rhr has a data character in th e non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. ? logic 0 = disable the receive data ready interrupt (default). ? logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable this bit enables the transmit ready interrupt which is issued whenever the thr becomes empty in the non- fifo mode or when data in the fifo fa lls below the programmed trigger level in the fifo mode. if the thr is empty when this bit is enabled, an in terrupt will be generated. reading isr will clear this interrupt. it is not necessary to disable this interrupt by setting ier bit-1 = 0. the uart will automatically issu e this interrupt again when more data is loaded into the fifo and t he fifo level drops below th e trigger level and/or it becomes empty. ? logic 0 = disable transmit ready interrupt (default). ? logic 1 = enable transmit ready interrupt. ier[2]: receive line status interrupt enable if any of the lsr register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in fifo. lsr bit-1 generates an interrupt immediately when the character has been received. lsr bits 2-4 generate an in terrupt when the character with errors is read out of the fifo. ? logic 0 = disable the receiver line status interrupt (default). ? logic 1 = enable the receiver line status interrupt. ier[3]: modem status interrupt enable ? logic 0 = disable the modem status register interrupt (default). ? logic 1 = enable the modem status register interrupt. ier[4]: sleep mode enable (requires efr bit-4 = 1) ? logic 0 = disable sleep mode (default). ? logic 1 = enable sleep mode. see sleep mode section for further details. ier[5]: xoff interrupt enable (requires efr bit-4=1) ? logic 0 = disable the software flow cont rol, receive xoff interrupt (default). ? logic 1 = enable the software flow control, receive xo ff interrupt. see software flow control section for details.
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 29 ier[6]: rts# output interrupt enable (requires efr bit-4=1) ? logic 0 = disable the rts# interrupt (default). ? logic 1 = enable the rts# interrupt. the uart issues an interrupt when the rts# pin makes a transition from low to high. ier[7]: cts# input interrupt enable (requires efr bit-4=1) ? logic 0 = disable the cts# interrupt (default). ? logic 1 = enable the cts# interrupt. the uart issues an interrupt when cts# pin makes a transition from low to high. 4.4 interrupt status register (isr) - read-only the uart provides multiple levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current hi ghest pending interrupt level to be se rviced, others are queued up to be serviced next. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source table, table 9 , shows the data values (bits 0-5) for the inte rrupt priority levels an d the interrupt sources associated with each of these interrupt levels. 4.4.1 interrupt generation: ? lsr is by any of the lsr bits 1, 2, 3 and 4. ? rxrdy is by rx trigger level. ? rxrdy time-out is by a 4-char plus 12 bits delay timer. ? txrdy is by tx trigger level or tx fifo empty (or transmitter empty in auto rs-485 control). ? msr is by any of the msr bits 0, 1, 2 and 3. ? receive xoff/special character is by det ection of a xoff or special character. ? cts# is when its transmitter toggles the input pin (from low to high) during auto cts flow control enabled by efr bit-7. ? rts# is when its receiver toggles th e output pin (from low to high) during auto rts flow control enabled by efr bit-6. 4.4.2 interrupt clearing: ? lsr interrupt is cleared by a read to the lsr register (b ut flags and tags not cleared until character(s) that generated the interrupt(s) has been emptied or cleared from fifo). ? rxrdy interrupt is cleared by reading data until fifo fa lls below the trigger level. ? rxrdy time-out interrupt is cleared by reading rhr until empty. ? txrdy interrupt is cleared by a read to the isr register or writing to thr. ? msr interrupt is cleared by a read to the msr register. ? xoff interrupt is cleared by a read to isr or when xon character(s) is received. ? special character interrupt is cleared by a read to isr or after the next character is received. ? rts# and cts# flow control interrupts are cleared by a read to the msr register.
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 30 ] isr[0]: interrupt status ? logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. ? logic 1 = no interrupt pending (default condition). isr[5:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority levels (see table 9 ). see ?section 4.4.1, interrupt generation:? on page 29 and ?section 4.4.2, interrupt clearing:? on page 29 for details. isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are disa bled. they are set to a logic 1 when the fifos are enabled. 4.5 fifo control register (fcr) - write-only this register is used to enable the fifos, clear the fi fos, set the transmit/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: fcr[0]: tx and rx fifo enable ? logic 0 = disable the transmit and receive fifo (default). ? logic 1 = enable the transmit and receive fifos. this bit must be set to logic 1 when other fcr bits are written or they will not be programmed. fcr[1]: rx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no receive fifo reset (default). ? logic 1 = reset the receive fifo pointers and fifo le vel counter logic (the rece ive shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. t able 9: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of interrupt l evel b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 1 0 0 0 1 1 0 lsr (receiver line status register) 2 0 0 1 1 0 0 rxrdy (receive data time-out) 3 0 0 0 1 0 0 rxrdy (received data ready) 4 0 0 0 0 1 0 txrdy (transmit ready) 5 0 0 0 0 0 0 msr (modem status register) 6 0 1 0 0 0 0 rxrdy (received xoff or special character) 7 1 0 0 0 0 0 cts#, rts# change of state - 0 0 0 0 0 1 none (default)
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 31 fcr[2]: tx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no transmit fifo reset (default). ? logic 1 = reset the transmit fifo pointers and fifo le vel counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[3]: dma mode select controls the behavior of the txrdy# and rxrdy# pins. see dma operation section for details. ? logic 0 = normal operation (default). ? logic 1 = dma mode. fcr[5:4]: transmit fifo trigger select (logic 0 = default, tx trigger level = 1) these 2 bits set the trigger level for the transmit fifo. the uart will issue a transmit interrupt when the number of characters in the fifo falls below the selected trigger level, or when it gets empty in case that the fifo did not get filled over the trigger level on last re-load. table 10 below shows the selections. efr bit-4 must be set to ?1? before these bits can be accessed. fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1) the fctr bits 5-4 are associated with these 2 bits. these 2 bits are used to set the trigger level for the receive fifo. the uart will issue a receive in terrupt when the number of the char acters in the fifo crosses the trigger level. table 10 shows the complete selections.
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 32 4.6 line control register (lcr) - read/write the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. t able 10: t ransmit and r eceive fifo t rigger t able and l evel s election t rigger t able fctr b it -5 fctr b it -4 fcr b it -7 fcr b it -6 fcr b it -5 fcr bit -4 r eceive t rigger l evel t ransmit t rigger l evel c ompatibility ta b l e - a 0 0 0 0 1 1 0 1 0 1 0 0 1 (default) 4 8 14 1 (default) 16c550, 16c2550, 16c2552, 16c554, 16c580 ta b l e - b 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 24 28 16 8 24 30 16c650a table-c 1 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 56 60 8 16 32 56 16c654 table-d 1 1 x x x x programmable via trg register. fctr[7] = 0. programmable via trg register. fctr[7] = 1. 16l2752, 16l2750, 16c2852, 16c854, 16c864 bit-1 bit-0 w ord length 0 0 5 (default) 0 1 6 1 0 7 1 1 8
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 33 lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bi t in conjunction with the programmed word length. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the pa rity bit is a simple way used in communications for data integrity check. see table 11 for parity select ion summary below. ? logic 0 = no parity. ? logic 1 = a parity bit is generated duri ng the transmission while the receiver checks for parity error of the data character received. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logi c 1, lcr bit-4 selects the even or odd parity format. ? logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format (default). ? logic 1 = even parity is gen erated by forcing an even numb er of logic 1?s in the tr ansmitted character. the receiver must be programmed to check the same format. lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit- 5 selects the forced parity format. ? lcr[5] = logic 0, parity is not forced (default). ? lcr[5] = logic 1 and lcr[4] = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. ? lcr[5] = logic 1 and lcr[4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. lcr[6]: transmit break enable when enabled, the break control bit causes a break cond ition to be transmitted (the tx output is forced to a ?space?, logic 0, state). this co ndition remains, until disabled by setting lcr bit-6 to a logic 0. ? logic 0 = no tx break condition (default). ? logic 1 = forces the transmitter output (tx) to a ?space ?, logic 0, for alerting the remote receiver of a line break condition. bit-2 w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2 t able 11: p arity selection lcr b it -5 lcr b it -4 lcr b it -3 p arity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity to mark, ?1? 1 1 1 forced parity to space, ?0?
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 34 lcr[7]: baud rate divisors enable baud rate generator divisor (dll/dlm) enable. ? logic 0 = data registers are selected (default). ? logic 1 = divisor latch registers are selected. 4.7 modem control register (mcr) or general purpose outputs control - read/write the mcr register is used for contro lling the serial/modem interface signal s or general pur pose inputs/outputs. mcr[0]: dtr# output the dtr# pin is a modem control outpu t. if the modem interface is not us ed, this output may be used as a general purpose output. ? logic 0 = force dtr# output to a logic 1 (default). ? logic 1 = force dtr# output to a logic 0. mcr[1]: rts# output the rts# pin is a modem control output and may be used for automatic hardware flow control by enabled by efr bit-6. if the modem interface is not used, this output may be used as a general purpose output. ? logic 0 = force rts# output to a logic 1 (default). ? logic 1 = force rts# output to a logic 0. mcr[2]: op1# output/auto rs485 control op1# is a general purpose output. if auto rs-485 mode is enabled, this works as the half-duplex direction control output. see fc tr[3] for more details. ? logic 0 = op1# output is at logic 1. ? logic 1 = op1# output is at logic 0. mcr[3]: op2# or irqn enable during pc mode op2# is a general purpose output available during the in tel bus interface mode of operation. in the pc bus mode, this bit enables the irqn operation. see pc mode section and irqn pin desc ription. the op2# output is not available in the pc mode. during intel bus mode operation: ? logic 0 = sets op2# output to a logic 1 (default). ? logic 1 = sets op2# output to a logic 0. during pc mode operation: see ta b l e 3 for more details. mcr[4]: internal loopback enable ? logic 0 = disable loopback mode (default). ? logic 1 = enable local loopback mode, see loopback section and figure 16 . mcr[5]: xon-any enable ? logic 0 = disable xon-any function (for 16c550 compat ibility, default). ? logic 1 = enable xon-any function. in this mode, any rx character rece ived will resume transmit operation. the rx character will be loaded into the rx fifo , unless the rx character is an xon or xoff character and the 850 is programmed to use the xon/xoff flow control. mcr[6]: infrared encoder/decoder enable ? logic 0 = enable the standard modem receive an d transmit input/output interface (default). ? logic 1 = enable infrared irda receive and transmit inputs/outputs. the tx/rx output/input are routed to the infrared encoder/decoder. the data input and output levels conform to the irda infrared interface requirement. while in this mode, th e infrared tx output will be a logic 0 during id le data conditions.
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 35 mcr[7]: clock prescaler select this bit overrides the clksel pi n selection available on the 48 and 52 pin packages. see figure 8 . ? logic 0 = divide by one. the input clock from the crystal or external clock is fed directly to the programmable baud rate generator without further modification, i.e., divide by one (default). ? logic 1 = divide by four. the prescaler divides the input clock from the crystal or external clock by four and feeds it to the programmable baud rate generator, hence, data rates become one fourth. 4.8 line status register (lsr) - read only this register provides the status of data transfers between the uart and the host. if ier bit-2 is set to a logic 1, an lsr interrupt will be generated immediately when any character in the rx fifo has an error (parity, framing, overrun, break). lsr[0]: receive data ready indicator ? logic 0 = no data in receive holding register or fifo (default). ? logic 1 = data has been received and is save d in the receive holding register or fifo. lsr[1]: receiver overrun error flag ? logic 0 = no overrun error (default). ? logic 1 = overrun error. a data overrun error condition occurred in the receive shift register. this happens when additional data arrives while the fi fo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the er ror. if ier bit-2 is set, an interrupt will be generated immediately. lsr[2]: receive data parity error tag ? logic 0 = no parity error (default). ? logic 1 = parity error. the receive character in rhr does not have correct parity information and is suspect. this error is associated with the charac ter available for reading in rhr. lsr[3]: receive data framing error tag ? logic 0 = no framing error (default). ? logic 1 = framing error. the receive character did not hav e a valid stop bit(s). this error is associated with the character available for reading in rhr. lsr[4]: receive break error tag ? logic 0 = no break condition (default). ? logic 1 = the receiver received a break signal (rx was a logic 0 for at least one character frame time). in the fifo mode, only one break character is loaded into the fifo. the break indication remains until the rx input returns to the idle condition, ?mark? or logic 1. lsr[5]: transmit holding register empty flag this bit is the transmit holding register empty indicator. the thr bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to th e transmit shift register. t he bit is reset to logic 0 concurrently with the data loading to the transmit holding r egister by the host. in the fifo mode this bit is set when the transmit fifo is empty, it is cleared when the transmit fifo contains at least 1 byte. lsr[6]: thr and tsr empty flag this bit is set to a logic 1 whenever the transmitter goes idle. it is set to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bi t is set to a logic 1 whenever the transmit fifo and transmit shift register are both empty.
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 36 lsr[7]: receive fifo data error flag ? logic 0 = no fifo error (default). ? logic 1 = a global indicator for the sum of all error bits in the rx fifo. at least one parity error, framing error or break indication is in the fifo data. this bit clears when there is no more error(s) in any of the bytes in the rx fifo. 4.9 modem status register (msr) - read only this register provides the current state of the modem interf ace input signals. lower four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a signal from the modem changes state. these bits may be used for general purpose inputs when they are not used with modem signals. msr[0]: delta cts# input flag ? logic 0 = no change on cts# input (default). ? logic 1 = the cts# input has changed state since the la st time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[1]: delta ds r# input flag ? logic 0 = no change on dsr# input (default). ? logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[2]: delta ri# input flag ? logic 0 = no change on ri# input (default). ? logic 1 = the ri# input has changed from a logic 0 to a logic 1, ending of the ringi ng signal. a modem status interrupt will be ge nerated if msr in terrupt is enabled (ier bit-3). msr[3]: delta cd# input flag ? logic 0 = no change on cd# input (default). ? logic 1 = indicates that the cd# input has changed st ate since the last time it was monitored. a modem status interrupt will be generated if ms r interrupt is enab led (ier bit-3). msr[4]: cts input status cts# pin may function as automatic hardware flow control signal input if it is enabled and selected by auto cts (efr bit-7). auto cts flow control allows starting and stopping of local data transmissions based on the modem cts# signal. a logic 1 on the cts# pin will stop uart transmitter as soon as the current character has finished transmission, and a logic 0 will resume data transmission. normally msr bit-4 bit is the compliment of the cts# input. however in the loopback mode, this bit is equivalent to the rts# bit in the mcr register. the cts# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status dsr# (active high, logical 1). normally this bit is the compliment of the dsr# input. in the loopback mode, this bit is equivalent to the dtr# bit in the mcr register. the dsr# input may be used as a general purpose input when the modem interface is not used. msr[6]: ri input status ri# (active high, logical 1). no rmally this bit is the compliment of the ri # input. in the loopback mode this bit is equivalent to bit-2 in the mcr register. the ri# i nput may be used as a general purpose input when the modem interface is not used. msr[7]: cd input status cd# (active high, logical 1). normally this bit is the co mpliment of the cd# input. in the loopback mode this bit is equivalent to bit-3 in the mcr register. the cd# i nput may be used as a general purpose input when the modem interface is not used. 4.10 scratch pad register (spr) - read/write
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 37 this is a 8-bit general purpose register for the user to store temporary data. the content of this register is preserved during sleep mode but becomes 0xff (default) after a reset or a power off-on cycle. 4.11 enhanced mode select register (emsr) this register replaces spr (during a write) and is accessible only when fctr[6] = 1. emsr[1:0]: receive/transmi t fifo count (write-only) when scratchpad swap (fctr[6]) is asserted, emsr bits 1-0 controls what mode the fifo level counter is operating in. during alternate rx/tx fifo counter mode, the first value read after emsr bits 1-0 have been asserted will always be the rx fifo counter. the second value read will correspond wit h the tx fifo counter. the next value will be the rx fifo counter again, then t he tx fifo counter and so on and so forth. emsr[7:2]: reserved 4.12 fifo level register (flvl) - read-only the fifo level register replaces the scratchpad regist er (during a read) when fctr[6] = 1. note that this is not identical to the fifo data count r egister which can be accessed when lcr = 0xbf. flvl[7:0]: fifo level register this register provides the fifo counter level for the rx fifo or the tx fifo or both depending on emsr[1:0]. see table 12 for details. 4.13 baud rate generator registers (dll and dlm) - read/write the concatenation of the contents of dlm and dll gives the 16-bit divisor value which is used to calculate the baud rate: ? baud rate = (clock frequency / 16) / divisor see mcr bit-7 and the baud rate table also. 4.14 device identification register (dvid) - read only this register contains the device id (0x10 for xr16c8 50). prior to reading this register, dll and dlm should be set to 0x00. 4.15 device revision register (drev) - read only this register contains the device revision information. for example, 0x01 means revision a. prior to reading this register, dll and dlm should be set to 0x00. 4.16 trigger level / fifo data c ount register (trg) - write-only user programmable transmit/receive trigger level register. trg[7:0]: trigger level register these bits are used to program desired trigger levels wh en trigger table-d is selected. fctr bit-7 selects between programming the rx trigger level (a logic 0) and the tx trigger level (a logic 1). 4.17 fifo data count regi ster (fc) - read-only t able 12: s cratchpad s wap s election fctr[6] emsr[1] emsr[0] scratchpad is 0 x x scratchpad 1 0 0 rx fifo counter mode 1 0 1 tx fifo counter mode 1 1 0 rx fifo counter mode 1 1 1 alternate rx/tx fifo counter mode
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 38 this register is accessible when lcr = 0xbf. note that th is register is not identical to the fifo level register which is located in the general regi ster set when fctr bit-6 = 1. fc[7:0]: fifo data count register transmit/receive fifo count. number of characters in transmit (fctr[7] = 1) or receive fifo (fctr[7] = 0) can be read via this register. 4.18 feature control regi ster (fctr) - read/write this register controls the xr16c2 850 new functions that are not ava ilable in st16c550 or st16c650a. fctr[1:0]: auto rts hysteresis user selectable rts# hysteresis levels for hardware flow control application. after reset, these bits are set to ?0? to select the next trigger leve l for hardware flow control. see ta b l e 5 for more details. fctr[2]: irda rx inversion ? logic 0 = select rx input as encoded irda data (idle state will be logic 0). ? logic 1 = select rx input as inverted enco ded irda data (idle state will be logic 1). fctr[3]: auto rs-485 direction control ? logic 0 = standard st16c550 mode. transmitter generates an interrupt when transmit holding register becomes empty and transmit shift register is shifting data out. ? logic 1 = enable auto rs485 direction control function . the direction control signal, rs485 pin, changes its output logic state from low to high one bit time after the last stop bit of the last character is shifted out. also, the transmit interrupt generation is delayed until the transmitter shift register becomes empty. the rs485 output pin will automatically return to a logic lo w when a data byte is lo aded into the tx fifo. fctr[5:4]: transmit/receive trigger table select see ta b l e 10 for more details. fctr[6]: scratchpad swap ? logic 0 = scratch pad register is selected as genera l read and write register. st16c550 compatible mode. ? logic 1 = fifo count register (read-only), enhanced mode select register (write-only). number of characters in transmit or receive fifo can be read vi a scratch pad register when this bit is set. enhanced mode select register is select ed when it is written into. t able 13: t rigger t able s elect fctr b it -5 fctr b it -4 t able 0 0 table-a (tx/rx) 0 1 table-b (tx/rx) 1 0 table-c (tx/rx) 1 1 table-d (tx/rx)
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 39 fctr[7]: programmable trigger register select ? logic 0 = registers trg and fc selected for rx. ? logic 1 = registers trg and fc selected for tx. 4.19 enhanced feature register (efr) enhanced features are enabled or disabled using this register. bit 0-3 provide si ngle or dual consecutive character software flow control selection (see table 14 ). when the xon1 and xon2 and xoff1 and xoff2 modes are selected, the double 8-bit words are concatenated in to two sequential characters. caution: note that whenever changing the tx or rx flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. efr[3:0]: software flow control select single character and dual sequential characters software flow control is supported. combinations of software flow control can be selected by programming these bits. efr[4]: enhanced function bits enable enhanced function control bit. this bit enables ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 to be modified. after modifying any enhanced bits, efr bit-4 can be set to a logic 0 to latch the new values. this feature prevents legacy software from altering or over writing the enhanced functions once set. normally, it is recommended to leave it enabled, logic 1. ? logic 0 = modification disable/latch en hanced features. ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are saved to retain the user settings. after a reset, the ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7are set to a logic 0 to be compatible with st16c550 mode (default). ? logic 1 = enables the above-mentioned register bits to be modified by the user. t able 14: s oftware f low c ontrol f unctions efr bit -3 c ont -3 efr bit -2 c ont -2 efr bit -1 c ont -1 efr bit -0 c ont -0 t ransmit and r eceive s oftware f low c ontrol 0 0 0 0 no tx and rx flow control (default and reset) 0 0 x x no transmit flow control 1 0 x x transmit xon1, xoff1 0 1 x x transmit xon2, xoff2 1 1 x x transmit xon1 and xon2, xoff1 and xoff2 x x 0 0 no receive flow control x x 1 0 receiver compares xon1, xoff1 x x 0 1 receiver compares xon2, xoff2 1 0 1 1 transmit xon1, xoff1 receiver compares xon1 or xon2, xoff1 or xoff2 0 1 1 1 transmit xon2, xoff2 receiver compares xon1 or xon2, xoff1 or xoff2 1 1 1 1 transmit xon1 and xon2, xoff1 and xoff2, receiver compares xon1 and xon2, xoff1 and xoff2 0 0 1 1 no transmit flow control, receiver compares xon1 and xon2, xoff1 and xoff2
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 40 efr[5]: special character detect enable ? logic 0 = special character detect disabled (default). ? logic 1 = special character detect enabled. the ua rt compares each incoming receive character with data in xoff-2 register. if a match exists, the receive data will be transfer red to fifo and isr bit-4 will be set to indicate detection of the special character. bit-0 co rresponds with the lsb bit of the receive character. if flow control is set for comparing xon1, xo ff1 (efr [1:0]= ?10?) then flow control and special character work normally. however, if flow control is set for comparing xon2, xoff2 (efr[1:0]= ?01?) then flow control works normally, but xoff2 will not go to the fifo, and will g enerate an xoff interrupt and a special character interrupt, if enabled via ier bit-5. efr[6]: auto rts flow control enable rts# output may be used for hardware flow control by setting efr bit-6 to logic 1. when auto rts is selected, an interrupt will be generated when the receive fifo is filled to the pr ogrammed trigge r level and rts de-asserts to a logic 1 at the next upper trigger level or h ysteresis level. rts# will re turn to a logic 0 when fifo data falls below the next lower tr igger level. the rts# output must be asserted (logic 0) before the auto rts can take effect. rts# pin will function as a gener al purpose ou tput when hardware flow control is disabled. ? logic 0 = automatic rts flow control is disabled (default). ? logic 1 = enable automatic rts flow control. efr[7]: auto cts flow control enable automatic cts flow control. ? logic 0 = automatic cts flow control is disabled (default). ? logic 1 = enable automatic cts flow control. data tr ansmission stops when cts# input de-asserts to logic 1. data transmission resumes wh en cts# returns to a logic 0. 4.20 software flow control registers (xoff1, xoff2, xon1, xon2) - read/write these registers are used as the prog rammable software flow control characters xoff1, xoff2, xon1, and xon2. for more details, see ta b l e 6 .
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 41 t able 15: uart reset conditions registers reset state dll bits 7-0 = 0xxx dlm bits 7-0 = 0xxx rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 fcr bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x00 mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 msr bits 3-0 = logic 0 bits 7-4 = logic levels of the inputs inverted spr bits 7-0 = 0xff emsr bits 7-0 = 0x00 flvl bits 7-0 = 0x00 efr bits 7-0 = 0x00 xon1 bits 7-0 = 0x00 xon2 bits 7-0 = 0x00 xoff1 bits 7-0 = 0x00 xoff2 bits 7-0 = 0x00 fc bits 7-0 = 0x00 i/o signals reset state tx logic 1 op1# logic 1 (intel bus mode) op2# logic 1 rts# logic 1 dtr# logic 1 rxrdy# logic 1 (intel bus mode) three-state condition (pc mode) txrdy# logic 0 (intel bus mode) three-state condition (pc mode) int logic 0 (intel bus mode) three-state condition (pc mode)
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 42 test 1: the following inputs should remain steady at vcc or gnd state to minimize sleep current: a0-a2, d0-d7, ior#, iow#, cs# and modem inputs. also, rx input must idle at lo gic 1 state while in sleep mode. in mixed voltage environ - ments, where the voltage at any of the inpu ts of the 651 is lower than its vcc supply voltage, the sleep current will be high - er than the maximum values given here. absolute maximum ratings power supply range 7 volts voltage at any pin gnd-0.3 v to 7 v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw typical package thermal resistance data ( margin of error : 15%) thermal resistance (48-tqfp) theta-ja =59 o c/w, theta-jc = 16 o c/w thermal resistance (44-plcc) theta-ja = 50 o c/w, theta-jc = 21 o c/w electrical characteristics dc electrical characteristics u nless otherwise noted : ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc = 2.97v to 5.5v s ymbol p arameter l imits 3.3v m in m ax l imits 5.0v m in m ax u nits c onditions v ilck clock input low level -0.3 0.6 -0.5 0.6 v v ihck clock input high level 2.4 vcc 3.0 vcc v v il input low voltage -0.3 0.8 -0.5 0.8 v v ih input high voltage (top mark date code of "ec yyww" and older) 2.0 vcc 2.2 vcc v v ih input high voltage (top mark date code of "f2 yyww and newer) 2.0 5.5 2.2 5.5 v v ol output low voltage 0.4 v i ol = 6 ma v ol output low voltage 0.4 v i ol = 4 ma v oh output high voltage 2.4 v i oh = -6 ma v oh output high voltage 2.0 v i oh = -1 ma i il input low leakage current 10 10 ua i ih input high leakage current 10 10 ua c in input pin capacitance 5 5 pf i cc power supply current 2.7 4 ma i sleep sleep current 30 50 ua see test 1
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 43 ac electrical characteristics ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.97v to 5.5v, 70 p f l oad where applicable s ymbol p arameter l imits 3.3v m in m ax l imits 5.0v m in m ax u nit clk clock pulse duration 45 30 ns osc crystal frequency (top mark date code "ec yyww" and older) 8 24 mhz osc crystal frequency (top mark date code "f2 yyww" and newer) 16 24 mhz osc external clock frequency (top mark date code "ec yyww" and older) 22 33 mhz osc external clock frequency (top mark date code "f2 yyww" and newer) 22 36 mhz tas address setup time (as# tied to gnd) 5 0 ns tah address hold time (as# tied to gnd) (top mark date code of "ec yyww" and older) 10 5 ns tah address hold time (as# tied to gnd) (top mark date code of "f2 yyww" and newer) 0 0 ns tcs chip select width 75 50 ns trd ior# strobe width 75 50 ns tdy read/write cycle delay 75 50 ns trdv data access time 35 25 ns tdd data disable time 0 25 0 15 ns twr iow# strobe width 75 50 ns tds1 data setup time (as# tied to gnd) 20 15 ns tdh1 data hold time (as# tied to gnd) 5 5 ns t asw address strobe width 75 50 ns t as1 address setup time (as# used) 5 5 ns t ah1 address hold time (as# used) 10 5 ns t as2 address setup time (as# used) 5 5 ns t ah2 address hold time (as# used) 10 5 ns t cs1 delay from chip select to as# 5 5 ns t csh delay from as# to chip select 10 5 ns t cs2 delay from as# to chip select 5 5 ns t rd1 delay from as# to read 10 5 ns
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 44 t rd2 delay from chip select to ior# 10 5 ns t dis delay from ior# to ddis# 20 10 ns t wr1 delay from as# to iow# 10 5 ns t ds2 data setup time (as# used) 20 15 ns t dh2 data hold time (as# used) 5 5 ns t as3 address setup time (pc mode) 10 5 ns t rd3 delay from aen# to ior# 10 5 ns t rd4 delay from ior# to aen# 10 5 ns t wr2 delay from aen# to iow# 10 5 ns t wr3 delay from iow# to aen# 5 5 ns t ds3 data setup time (pc mode) 20 15 ns t dh3 data hold time (pc mode) 5 5 ns twdo delay from iow# to output 75 50 ns tmod delay to set interrupt from modem input 75 50 ns trsi delay to reset interrupt from ior# 75 50 ns tssi delay from stop to set interrupt 1 1 bclk trri delay from ior# to reset interrupt 75 50 ns tsi delay from stop to interrupt 75 50 ns tint delay from initial int re set to transmit start 8 24 8 24 bclk twri delay from iow# to reset interrupt 75 50 ns tssr delay from stop to set rxrdy# 1 1 bclk trr delay from ior# to reset rxrdy# 75 50 ns twt delay from iow# to set txrdy# 75 50 ns tsrt delay from center of start to reset txrdy# 8 8 bclk trst reset pulse width 40 40 ns n baud rate divisor 1 2 16 -1 1 2 16 -1 - bclk baud clock 16x hz ac electrical characteristics ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.97v to 5.5v, 70 p f l oad where applicable s ymbol p arameter l imits 3.3v m in m ax l imits 5.0v m in m ax u nit
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 45 f igure 17. c lock t iming f igure 18. m odem i nput /o utput t iming osc clk clk external clock iow # iow rts# dtr# cd# cts# dsr# int ior# ior ri# twdo tmod tmod trsi tmod active active change of state change of state active active active change of state change of state change of state active active
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 46 f igure 19. d ata b us r ead t iming in i ntel b us m ode with as# tied to gnd f igure 20. d ata b us w rite t iming in i ntel b us m ode with as# tied to gnd t as t dd t ah t rd t rdv t dy t dd t rdv t ah t as t cs valid address valid address valid data valid data a0-a2 cs2# ior# d0-d7 t cs t rd cs0 cs1 ior note: only one chipselect and one read strobe should be used. t as t dh2 t ah t wr t ds2 t dy t dh2 t ds2 t ah t as t cs valid address valid address valid data valid data a0-a2 cs2# iow# d0-d7 t cs t wr cs1 cs0 iow note: only one chipselect and one write strobe should be used.
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 47 f igure 21. d ata b us r ead t iming in i ntel b us m ode using as# f igure 22. d ata b us w rite t iming in i ntel b us m ode using as# t as1 t dd t ah1 t rd t rdv t dy valid address valid data a0-a2 cs2# ior# d0-d7 t cs cs0 or cs1 ior as# t asw t cs1 t csh t rd1 ddis# t asw valid address t cs t ah2 t csh t dis t rd2 t rd t dis t rdv valid data t dd t as2 t cs2 note: only one chipselect and one read strobe should be used. t as1 t dh2 t ah1 t wr t ds2 t dy valid address valid data a0-a2 cs2# iow# d0-d7 t cs cs0 or cs1 iow as# t asw t cs1 t csh t wr1 t asw valid address t cs t ah1 t csh t wr1 t wr valid data t dh2 t as2 t cs1 t ds2 note: only one chipselect and one write strobe should be used.
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 48 f igure 23. d ata b us r ead t iming in pc m ode f igure 24. d ata b us w rite t iming in pc m ode t as3 t dd t rd4 t rd t rdv t dy t dd t rdv t rd4 t as3 t cs valid address valid address valid data valid data a0-a9 aen# ior# d0-d7 rdtm t cs t rd t rd3 t rd3 t as3 t dh t wr3 t wr t ds t dy t dh t ds t wr3 t as3 t cs valid address valid address valid data valid data a0-a9 aen# iow# d0-d7 t cs t wr t wr2 t wr2
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 49 f igure 25. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] f igure 26. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] rx rxrdy# ior# int d0:d7 start bit d0:d7 stop bit d0:d7 t ssr 1 byte in rhr active data ready active data ready active data ready 1 byte in rhr 1 byte in rhr t ssr t ssr rxnfm t rr t rr t rr t ssr t ssr t ssr (reading data out of rhr) tx txrdy# iow# int* d0:d7 start bit d0:d7 stop bit d0:d7 t wt txnonfifo t wt t wt t wri t wri t wri t srt t srt t srt *int is cleared when the isr is read or when data is loaded into the thr. isr is read isr is read isr is read (loading data into thr) (unloading) ier[1] enabled
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 50 f igure 27. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] f igure 28. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] rx rxrdy# ior# int d0:d7 s t ssr rxintdma# rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties first byte is received in rx fifo d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo) rx rxrdy# ior# int d0:d7 s t ssr rxfifodma rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo)
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 51 f igure 29. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] f igure 30. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] tx txrdy# iow# int* txdma# d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri (unloading) (loading data into fifo) last data byte transmitted tx fifo fills up to trigger level tx fifo drops below trigger level data in tx fifo tx fifo empty t wt t srt tx fifo empty t t s t si isr is read ier[1] enabled isr is read *int is cleared when the isr is read or when tx fifo fills up to the trigger level. tx txrdy# iow# int* d0:d7 s txdma d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri t (unloading) (loading data into fifo) last data byte transmitted tx fifo fills up to trigger level tx fifo drops below trigger level at least 1 empty location in fifo t srt tx fifo full t wt t si isr read isr read *int cleared when the isr is read or when tx fifo fills up to trigger level. ier[1] enabled
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 52 package dimensions (48 pin tqfp - 7 x 7 x 1 mm ) note: the control dimensio n is the millimeter column inches millimeters symbol min max min max a 0.039 0.047 1.00 1.20 a1 0.002 0.006 0.05 0.15 a2 0.037 0.041 0.95 1.05 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.346 0.362 8.80 9.20 d1 0.272 0.280 6.90 7.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 0 7 0 7 36 25 24 13 1 1 2 37 48 d d 1 d d 1 b e a 2 a 1 a seating plane l c
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo 53 package dimensions (44 pin plcc) note: the control dimensio n is the millimeter column inches millimeters symbol min max min max a 0.165 0.180 4.19 4.57 a1 0.090 0.120 2.29 3.05 a2 0.020 --- 0.51 --- b 0.013 0.021 0.33 0.53 b 1 0.026 0.032 0.66 0.81 c 0.008 0.013 0.19 0.32 d 0.685 0.695 17.40 17.65 d1 0.650 0.656 16.51 16.66 d 2 0.590 0.630 14.99 16.00 d 3 0.500 typ. 12.70 typ. e 0.050 bsc 1.27 bsc h 1 0.042 0.056 1.07 1.42 h 2 0.042 0.048 1.07 1.22 r 0.025 0.045 0.64 1.14 44 lead plastic leaded chip carrier (plcc) rev. 1.00 1 d d 1 a a 1 d d 1 d 3 b a 2 b 1 e seating plane d 2 244 d 3 c r 45 x h 2 45 x h 1
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 54 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and schedules contai ned here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2005 exar corporation datasheet august 2005. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. revision history d ate r evision d escription february 2000 rev 1.0.0 initial datasheet. april 2002 rev 2.0.0 changed to standard style format. internal registers are described in the order they are listed in the internal register table. clarified timing diagrams. corrected auto rts hysteresis table. renamed rclk (rec eive clock) to bclk (baud clock) and tim - ing symbols. added t ah , t cs and osc. january 2003 rev 2.1.0 changed to single column format. added factory test mode description and work- around. may 2003 rev 2.1.1 corrected patent number on first page. june 2003 rev 2.2.0 added and updated device status in ordering information: 40-pin pdip and 52-pin qfp are discontinued. march 2004 rev 2.3.0 devices with top mark date code of "f2 yyww" and newer have 5v tolerant inputs (except for xtal1) and have 0 ns address hold time (t ah ). factory test mode entry ( see?factory test mode? on page 7. ) was improved and drev register was updated to 0x06. in addition, the packages are now in green molding compound. august 2005 rev 2.3.1 removed discontinued packages (40-pin pdip and 52-pin qfp) from ordering infor - mation.
xr xr16c850 rev. 2.3.1 2.97v to 5.5v uart with 128-byte fifo i table of contents general description........ ................. ................ ................ ............... .............. ........... 1 f eatures ............................................................................................................................... ...................... 1 a pplications ............................................................................................................................... ................ 1 f igure 1. b lock d iagram ............................................................................................................................... .............................. 1 f igure 2. p inouts i n i ntel b us m ode a nd pc m ode , tqfp a nd plcc p ackages ................................................................... 2 pin descriptions ............. ................ ................ ................. ................ ................. ........... 3 intel bus mode interface. the sel pin is connected to vcc. ..................................................................... ................ 3 ordering information ............................................................................................................................... .3 pc mode interface signals. connect sel pin to gnd to se lect pc mode. ........ .............. .............. ........... ............ ..... 5 modem or serial i/o interface .................................................................................................. ..................... 6 ancillary signals .............................................................................................................. .................................. 6 1.0 product description ..................................................................................................... ............... 8 2.0 functional descriptions ................................................................................................. ........... 9 2.1 host data bus interface ................................................................................................. ...................... 9 f igure 3. xr16c850 i ntel b us i nterconnections .................................................................................................................... 9 f igure 4. xr16c850 pc m ode i nterconnections ...................................................................................................................... 9 2.2 pc mode ................................................................................................................. ....................................... 10 t able 1: pc m ode i nterface o n - chip a ddress d ecoder and i nterrupt s election .............................................................. 10 f igure 5. pc m ode i nterface in an e mbedded a pplication ..................................................................................................... 10 2.3 16-bit bus interface .................................................................................................... ........................... 11 f igure 6. xr16c850 16-b it b us i nterface .............................................................................................................................. 1 1 2.4 5-volt tolerant inputs .... .............. .............. .............. .............. .............. .............. .......... ....................... 11 2.5 device reset ..... .............. .............. .............. .............. .............. ........... ........... ........... .................................. 11 2.6 device identification and revision ........... ........................................................................... ............ 11 2.7 internal registers ...................................................................................................... ........................... 12 2.8 dma mode ................................................................................................................ .................................... 12 t able 2: txrdy# and rxrdy# o utputs in fifo and dma m ode ........................................................................................... 12 2.9 interrupts .............................................................................................................. ................................... 13 t able 3: i nterrupt o utput f unctions ............................................................................................................................... ....... 13 f igure 7. t ypical oscillator connections ............................................................................................................................... 13 2.10 crystal oscillator or external clock ................................................................................... .. 13 2.11 programmable baud rate generat or .............. .............. .............. ........... ........... ........... ............ .. 14 f igure 8. b aud r ate g enerator ............................................................................................................................... ................ 14 t able 4: t ypical data rates with a 14.7456 mh z crystal or external clock ...................................................................... 14 2.12 transmitter ....... .............. .............. .............. .............. ........... ........... ........... ............ ................................. 15 2.12.1 transmit holding register (thr) - write only.......................................................................... ............. 15 2.12.2 transmitter operatio n in non-fifo mode ................................................................................ ................ 15 f igure 9. t ransmitter o peration in non -fifo m ode .............................................................................................................. 15 2.12.3 transmitter operation in fifo mode .................................................................................... ..................... 15 f igure 10. t ransmitter o peration in fifo and f low c ontrol m ode ................................................................................... 16 2.13 receiver ............................................................................................................... ..................................... 16 2.13.1 receive holding register (rhr) - read-only ............................................................................ .............. 16 f igure 11. r eceiver o peration in non -fifo m ode .................................................................................................................. 17 f igure 12. r eceiver o peration in fifo and a uto rts f low c ontrol m ode ....................................................................... 17 2.14 auto rts (hardware) flow co ntrol ............... .............. .............. ........... ........... ............ .......... ...... 18 2.15 auto rts hysteresis ................................................................................................... ........................ 18 t able 5: a uto rts h ysteresis ............................................................................................................................... ................... 18 2.16 auto cts (hardware ) flow control .............. .............. .............. ........... ........... ............ .......... ...... 19 f igure 13. a uto rts and cts f low c ontrol o peration ....................................................................................................... 19 2.17 auto xon/xoff (software) flow control .................................................................................. . 20 t able 6: a uto x on /x off (s oftware ) f low c ontrol ............................................................................................................... 20 2.18 special character detect .. .............. .............. .............. .............. .............. ........... ........... ................. 20 2.19 auto rs485 half-duplex control ........................................................................................ .......... 20 f igure 14. a uto rs-485 h alf -d uplex c ontrol ....................................................................................................................... 21 2.20 infrared mode ..... .............. .............. .............. .............. .............. ........... ........... ......... .............................. 21 f igure 15. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding .......................................................................... 22 2.21 sleep mode with auto wake-u p ............. .............. .............. .............. .............. ........... .......... ............ 23 2.22 internal loopback ..................................................................................................... ......................... 24 f igure 16. i nternal l oopback ............................................................................................................................... .................... 24
xr16c850 xr 2.97v to 5.5v uart with 128-byte fifo rev. 2.3.1 ii 3.0 uart internal registers ................................................................................................. ..........25 t able 7: xr16c850 uart internal registers .......................................................................................... ....................... 25 t able 8: internal registers description. s haded bits are enabled when efr b it -4=1......................................... 26 4.0 internal register descriptions .......................................................................................... ...27 4.1 receive holding register (rhr) - read- only .. .............. .............. .............. ........... ............ .......... .. 27 4.2 transmit holding register (thr) - write-only ............................................................................ 27 4.3 interrupt enable register (ier ) - read/write .......... .............. .............. .............. .............. .......... .. 27 4.3.1 ier versus receive fifo interrupt mode operation ....................................................................... ...... 27 4.3.2 ier versus receive/transmit fifo polled mode operation ................................................................ 28 4.4 interrupt status register (isr) - read-only ............................................................................. .. 29 4.4.1 interrupt generation: .................................................................................................. .................................... 29 4.4.2 interrupt clearing: .................................................................................................... ....................................... 29 t able 9: i nterrupt s ource and p riority l evel ....................................................................................................................... 30 4.5 fifo control register (fcr) - write-only ................................................................................ ...... 30 t able 10: t ransmit and r eceive fifo t rigger t able and l evel s election .......................................................................... 32 4.6 line control register (lcr) - read/write ................................................................................ ...... 32 t able 11: p arity selection ............................................................................................................................... ......................... 33 4.7 modem control register (mcr) or gene ral purpose outputs control - read/write 34 4.8 line status register (lsr) - read only .................................................................................. ......... 35 4.9 modem status register (msr) - read only ................................................................................. ... 36 4.10 scratch pad register (spr) - read/write ................................................................................ .... 36 4.11 enhanced mode select register (emsr) ................................................................................... ... 37 t able 12: s cratchpad s wap s election ............................................................................................................................... ..... 37 4.12 fifo level register (flvl) - read-only ................................................................................. ......... 37 4.13 baud rate generator registers (dll and dlm) - read/write ...... ........... ........... ........... ....... 37 4.14 device identification register (dvid) - read only .................................................................... 3 7 4.15 device revision register (drev) - read only ............................................................................ .. 37 4.16 trigger level / fifo data co unt register (trg) - wr ite-only ....... .............. ............... ......... 37 4.17 fifo data count register (fc) - read-only .............................................................................. .... 37 4.18 feature control register (fctr) - read/write ........................................................................ 3 8 t able 13: t rigger t able s elect ............................................................................................................................... ................. 38 4.19 enhanced feature register (efr) ........................................................................................ .......... 39 t able 14: s oftware f low c ontrol f unctions ........................................................................................................................ 39 4.20 software flow control registers (xoff1, xoff2, xon1, xon2) - read/write ................ 40 t able 15: uart reset conditions .................................................................................................... .................................. 41 absolute maximum ratings........... ................ ................ ............... .............. ...........42 t ypical package thermal resistance data ( margin of error : 15%)..................................................42 electrical characteristics ........ ................ ................ ............... .............. ...........42 dc e lectrical c haracteristics ..............................................................................................................42 ac e lectrical c haracteristics ..............................................................................................................43 ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.97v to 5.5v, 70 p f l oad where applicable ............................................................................................................................... ...................43 f igure 17. c lock t iming ............................................................................................................................... .............................. 45 f igure 18. m odem i nput /o utput t iming ............................................................................................................................... ..... 45 f igure 19. d ata b us r ead t iming in i ntel b us m ode with as# tied to gnd ......................................................................... 46 f igure 20. d ata b us w rite t iming in i ntel b us m ode with as# tied to gnd ........................................................................ 46 f igure 22. d ata b us w rite t iming in i ntel b us m ode using as#............................................................................................ 47 f igure 21. d ata b us r ead t iming in i ntel b us m ode using as# ............................................................................................. 47 f igure 24. d ata b us w rite t iming in pc m ode ........................................................................................................................ 48 f igure 23. d ata b us r ead t iming in pc m ode .......................................................................................................................... 48 f igure 25. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] ............................................................................................ 49 f igure 26. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] .......................................................................................... 49 f igure 27. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] .......................................................................... 50 f igure 28. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] ........................................................................... 50 f igure 29. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] .............................................................. 51 f igure 30. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ]............................................................... 51 p ackage d imensions (48 pin tqfp - 7 x 7 x 1 mm )....................................................................................52 p ackage d imensions (44 pin plcc) .........................................................................................................53 t able of c ontents ................ ................. ................ ................ ............... .............. .............. i

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